The present invention relates to improvements in a displacement detecting apparatus.
Conventionally, a typical displacement detecting apparatus of an electromagnetic modulation type has obtained a displacement by converting two parallel modulation signals indicative of a detection result into a phase modulation signal and by comparing the cycle of the phase modulation signal with the cycle of a reference signal. In order to improve the detection accuracy of the detected displacement, an interpolation has been executed as explained hereinafter with reference to FIGS. 6 and 7. In FIG. 6, the phase modulation signal is inputted to an input terminal T51 and is differentiated at a differentiating circuit 501. The differentiating circuit 501 outputs a pulse at an end of a fall of the phase modulation signal and applies it to a clear terminal of an up counter 502 and a reverse circuit RV3. The reversed signal from the reverse circuit RV3 is applied to a register 503 and a preset command input port of a down counter 506. After the up counter 502 is cleared by receiving the pulse from the differentiating circuit 501, the up counter 502 calculates an interpolation clock supplied from a terminal T52 and incrementally counts until again cleared. The register 503 latches the count value of the up counter 502 when the register 503 receives the reverse signal of the pulse from the differentiating circuit 501 reversed at the reverse circuit RV3. Accordingly, the count value is a value obtained by dividing the cycle of the phase modulation signal with the cycle of the interpolation clock. In other words, it is a pulse number of the interpolation clock corresponding to the length of the cycle of the phase modulation signal. The interpolation number to be applied to the system is set at an interpolation number setting device 504. In this case, a value obtained by dividing the cycle of the reference signal with the cycle of the interpolation clock is used as the interpolation number. For example, a value 200 is obtained by dividing the cycle 20 .mu.sec of the reference signal with the cycle 0.1 .mu.sec of the interpolation clock and is used as the interpolation number. A signed subtracter 505 receives a signal A which is obtained by dividing the cycle of the phase modulation signal with the cycle of the interpolation clock such as 220=22 .mu.sec.div.0.1 .mu.sec and a signal B which is obtained by dividing the cycle of the reference signal with the cycle of the interpolation clock such as 200. The signed subtracter 505 obtains a direction signal S indicating a direction of the displacement and a displacement signal (.vertline.A-B.vertline., herein 20=220-200) by subtracting the signal B from the signal A.
The displacement signal represents the displacement by means of a pulse number of the interpolation clock. The pulse number indicative of the displacement is used as preset data of a down counter 506. The down counter 506 is provided with an input terminal for receiving the preset command, an input terminal for receiving the preset data, an input terminal for receiving the clock signal and an output terminal for outputting a borrow signal.
When the signal from the reverse circuit RV3 is applied to the preset command terminal of the down counter 506, the down counter 506 sets the displacement signal .vertline.A-B.vertline. applied from the signed subtracter 505 as a count value and outputs the borrow signal. The borrow signal is applied to an input port of a gate circuit NAND3 to control the passing of the clock signal applied to the other port of the gate circuit NAND3. The operation of the down counter 506 will be briefly discussed with reference to FIG. 7. It is assumed that the preset data is 4, 3 and 3 as shown in FIG. 7. The signal obtained by differentiating the phase modulation signal inputted to the terminal T51 at the differentiating circuit 501 and by reversing the differentiated signal at the reverse circuit RV3 represents the fall point of the phase modulation signal. The point represents an end of a cycle of the phase modulation signal and a start of the next cycle. That is, the preset command at the down counter 506 represents a start of each cycle. When the down counter 506 receives the preset command, it presets the preset data therein and turns the borrow signal ON, as shown by FIG. 7. When the borrow signal is turned ON, the gate circuit NAND3 is opened to output the basic clock signal to A/B phase converter and to the down counter 506. Upon receipt of the clock signal, the down counter 506 starts the count down of the count value (herein, 4), as shown in FIG. 7. When the preset data is 4, the pulse number of the basic clock passing through the gate circuit NAND3 is four. Therefore, the down counter 506 counts four pulses, and the content of the counter is changed to 4, 3, 2, 1, and 0. When the count value of the counter 506 reaches zero, the borrow signal is turned OFF, and the output of the pulse is stopped by closing the gate circuit NAND3. When the next displacement signal (preset data, 3) is set at the down counter 506, again similar operation is repeated. In the above-mentioned operation, although the magnitude of the displacement is represented by the number of the pulses, the down counter 506 operates synchronously with the basic clock. Therefore, the clock sent to the A/B phase converter through the gate circuit NAND3 has the cycle of the basic clock, and has the number of pulses as the number of pulses of the interpolation clock corresponding to the displacement. The later A/B phase converter is constituted by a first flip-flop FF1, a second flip-flop FF2, a first gate circuit NAND1, a second gate circuit NAND2, a first OR circuit OR1, a second OR circuit OR2 and a reverse circuit RV1. The direction signal S from the subtracter 505 is inputted to one input port of the first OR circuit OR1. The output of the first OR circuit OR1 is inputted to an input port of the gate circuit NAND1 and is reversed at the reverse circuit RV1. The reversed signal is inputted to an input port of the second gate circuit NAND2. The clock pulse passed through the gate circuit NAND3 is inputted to another input port of each of the first and second gate circuit NAND1 and NAND2. Therefore, the clock pulse is inputted through an opened gate according to the polarity of the direction signal to the corresponding flip-flop FF1 or FF2 to reverse its condition. The outputs of the first and second flip-flops FF1 and FF2 are supplied to the terminals T53 and T54 as the A-phase signal and the B-phase signal, respectively. The output of the flip-flop FF1, FF2 is applied to an input port of the second OR circuit OR2, and the output of the second OR circuit OR is applied to the other input port of the first OR circuit OR1. Therefore, the clock pulse supplied from the gate circuit NAND3 through the reverse circuit RV2 to the A/B converter passes the first and second gate circuits NAND1 and NAND2 alternatively, and reversed A-phase signal and B-phase signal are alternatively outputted to the output terminals T53 and T54, as shown in FIG. 8. In case that the displacement is 4 as shown at the left side hand of FIG. 8, the first flip-flop FF1 is reversed by the first pulse, and the A-phase signal becomes L (low level). The second flip-flop FF2 is reversed by the second pulse, and the B-phase signal becomes L. Further, the first flip-flop FF1 is again reversed by the third pulse, and the A-phase signal becomes H (high level). The second flip-flop FF2 is again reversed by the final fourth pulse, and the B-phase signal becomes H. Thereafter, the A-phase and B-phase signals are not changed until the next cycle.
However, the method does not have a part for making clear a positional relation between the origin point and A/B phase or ABS value of the cyclic displacement information within one cycle obtained by the displacement sensor. Therefore, when the electric source is turned on, the condition of the A/B phase signal (2 bit Glay code) is unstable (does not become constant). This is not sufficient to respond to the today's demand that it is preferable to synchronize the origin signal with the A/B phase signal.